1. Field of the Invention
The present invention relates to a PLL (Phase-Locked Loop) clock signal generation circuit, and it particularly relates to technology for increasing stable operation region (lock range).
2. Description of the Related Art
In the increasing demands for an IC card in the recent years, there has been a strong request for stable operations of an integrated PLL clock signal generation circuit even in a wide variation range of a standard clock input from outside the circuit, thus involving an increase of lock range of the PLL clock signal generation circuit.
FIG. 5 shows configuration of a basic PLL clock signal generation circuit. The PLL clock signal generation circuit includes a phase comparator 101, a charge pump circuit 102, a filter circuit 103, a voltage control oscillator 104, a first frequency divider 501 and a second frequency divider 502. An outline for the operation of each of the circuit will be described bellow.
The phase comparator 101 is fed with a standard clock from outside, and a comparative clock of which output frequency of the voltage control oscillator 104 is divided by the second frequency divider 502. The phases of the two clocks are compared at the phase comparator 101. When the phase of the comparative clock delays compared with the phase of the standard clock, the circuit outputs the UP signal by amount equal to the delay. On the other hand, when the phase of the comparative clock proceeds to a phase of the standard clock, the circuit outputs the DOWN signal by amount equal to the proceedings. These UP signal and DOWN signal are integrated through the charge pump circuit 102 and the filter circuit 103. The voltage integrated by the UP signal rises, and the voltage integrated by the DOWN signal falls. Integrated voltage becomes reference voltage for changing the oscillation frequency of the voltage control oscillator 104.
The voltage control oscillator 104 includes a ring oscillator circuit that uses an inverter of odd numbered stage such as three stages, five stages, etc. In this configuration, the oscillation frequency can be changed by changing the input voltage. More specifically, the increase in the input voltage of the voltage control oscillator 104 causes increase in the output oscillation frequency of the voltage control oscillator 104, and the decrease in the input voltage of the voltage control oscillator 104 causes the decrease in the output oscillation frequency of the voltage control oscillator 104. The output clock of the voltage control oscillator 104 is divided at the second frequency divider 502 to be comparative clock and is input to the phase comparator 101 together with standard clock. Therefore, the output of the voltage control oscillator 104 is the oscillation frequency of the predetermined multiple rate (1/(ratio of division)) of the standard clock when the PLL clock signal generation circuit is locked to ensure stable operation. When the output clock of the voltage control oscillator 104 is used as system clock of a semi conductor device, the output clock is used as internal clock after separately divided by the first frequency divider 501.
FIG. 6 shows a relationship between input (reference) voltage of the voltage control oscillator 104 and oscillation frequency which is the output signal of the voltage control oscillator 104. It is divided into three states, those are, the first state, the second state and the third state according to the voltage range of the reference voltage. In the first state, the oscillation frequency marks a point below a lower limit of the operation of the voltage control oscillator 104, and does not change (under saturation condition) as the reference voltage changes. In the second state, the oscillation frequency changes as the reference voltage. In the third state, the oscillation frequency marks a point above an upper limit of the operation of the voltage control oscillator 104, and does not change (under saturation condition) as the reference voltage changes. In the second state, with respect to changes of the standard clock, the comparative clock can be matched to ensure a stable operation (lock) of the PLL clock signal generation circuit, which is referred to as a region capable of locking (or a lock range).
As shown in FIG. 6, VCL shows the reference voltage that outputs the oscillation frequency of the lower limit operation of the voltage control oscillator 104, while VCH shows the reference voltage that outputs the oscillation frequency of the upper limit operation of the voltage control oscillator 104.
In the increasing demand for an IC card in the recent years, there has been a strong request to handle the input of standard clock frequency with a wide frequency range, thus increase of the lock range of PLL clock signal generation circuit is necessary. As a prior art for increasing the lock range, Japanese Unexamined Patent Publication No. 6-326603, for example, is disclosed.
A prior art for increasing a lock range disclosed in the Japanese Unexamined Patent Publication No. 6-326603 will be described below with reference of FIG. 10.
As shown in FIG. 10, the PLL clock signal generation circuit of the prior art includes a phase comparator 11 that generates error voltage due to the phase difference, a low-pass filter 12, a voltage control oscillator 13 and a programmable N counter 14. This circuit uses one voltage control oscillator 13 and provides a frequency changer 15 (a 2n programmable divider is used in the following embodiment) between the one voltage control oscillator 13 and the programmable N counter 14. In the case where a 2n programmable divider n=0, the operation of the circuit configuration is such that the oscillation frequency fs of the voltage control oscillator 13 is N divided by the programmable N counter 14 to generate a frequency fv (wherein fv=fs/N) and is input to the phase comparator 11 together with the input signal of the standard clock fr. The phase comparator 11 generates error voltage according to the phase difference between the standard frequency fr and the divided frequency fv of the N division counter. The output error voltage from the phase comparator 11 becomes the control voltage of the voltage control oscillator 13 by cutting off the high frequency components at the low pass filter 12. The control voltage is provided to narrow the difference between the divided frequency fv of the oscillation frequency fs of the voltage control oscillator 13 and the standard clock fr. When the difference between the frequency fv and the standard clock fr is zero (0), the circuit is under a locked condition, and the relation between the frequency fv and the standard clock fr can be expressed by the following equation (1). When the 2n programmable divider n=0, and the output frequency f0 expressed in the equation (3) is used, the relationship can be expressed by the equation (2).fr=fv=fs/N  (1)fr=fv=f0/N  (2)f0=N×fr  (3)
When the region where oscillation is available in the output frequency f0 is expressed with a minimum oscillation frequency fmin and a maximum oscillation frequency fmax, the region can be expressed in the equation (4) through (6) according to the value n of the 2N programmable divider which is a frequency changer 15.f0=fmin through fmax: n=0  (4)f0=fmin/2 through fmax/2: n=1  (5)f0=fmin/4 through fmax/4: n=2  (6)
From the above, the output of the frequency changer 15 is changeable by a value of n so that a wider range of output frequency can be obtained.
However, the PLL clock signal generation circuit in the prior art disclosed in the Japanese Unexamined Patent Publication No. 6-326603 requires the n value of the frequency changer 15 (2N programmable divider) to be set to stretch the lock range. The n value should be set from the CPU which controls the PLL clock signal generation circuit and is mounted outside the PLL clock signal generation circuit. In order to handle the change of the standard clock, the clock should be observed by the CPU and the n value should be changed according to the change of the standard clock. This increases the load to the CPU.
The CPU process in the IC card ranges widely such as the data communication. Thus it is important to reduce the load to the CPU as much as possible. The circuit which observes the changes occurring at the standard clock needs to be configured.